? semiconductor components industries, llc, 2009 august, 2009 ? rev. 1 1 publication order number: cat24aa04/d cat24aa04, cat24aa08 4-kb and 8-kb i 2 c cmos serial eeprom description the cat24aa04/24aa08 are 4 ? kb and 8 ? kb cmos serial eeprom devices internally organized as 512x8/1024x8 bits. they feature a 16 ? byte page write buffer and support 100 khz, 400 khz and 1 mhz i 2 c protocols. in contrast to the cat24c04/24c08, the cat24aa04/24aa08 have no external address pins, and are therefore suitable in applications that require a single cat24aa04/08 on the i 2 c bus. features ? standard and fast i 2 c protocol compatible ? supports 1 mhz clock frequency ? 1.7 v to 5.5 v supply voltage range ? 16 ? byte page write buffer ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? tsot ? 23 5 ? lead and soic 8 ? lead packages ? these devices are pb ? free, halogen free/bfr free, and rohs compliant sda scl wp cat24aa08 cat24aa04 v cc v ss figure 1. functional symbol http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information pin configurations sda scl wp v cc v ss nc nc nc 1 (top view) soic ? 8 w suffix case 751bd tsot ? 23 tb suffix case 419ae 2 3 4 8 7 6 5 v cc wp sda v ss scl 1 (top view) 2 3 5 4 soic tsot ? 23 pin function pin name sda function serial data/address scl clock input wp write protect v cc power supply v ss ground nc no connect
cat24aa04, cat24aa08 http://onsemi.com 2 table 1. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the dc input voltage on any pin should not be lower than ? 0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than ? 1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. table 2. reliability characteristics (note 2) symbol parameter min units n end (note 3) endurance 1,000,000 program/erase cycles t dr data retention 100 years 2. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec ? q100 and jedec test methods. 3. page mode @ 25 c table 3. d.c. operating characteristics ( v cc = 1.7 v to 5.5 v, t a = ? 40 c to 85 c, unless otherwise speci ed.) symbol parameter test conditions min max units i ccr read current read, f scl = 400 khz 0.5 ma i ccw write current write, f scl = 400 khz 1 ma i sb standby current all i/o pins at gnd or v cc 1 a i l i/o pin leakage pin at gnd or v cc 1 a v il input low voltage ? 0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0 ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0 ma 0.2 v table 4. pin impedance characteristics (v cc = 1.7 v to 5.5 v, t a = ? 40 c to 85 c, unless otherwise speci ed.) symbol parameter conditions max units c in (note 2) sda i/o pin capacitance v in = 0 v 8 pf c in (note 2) input capacitance (other pins) v in = 0 v 6 pf i wp (note 4) wp input current v in < 0.5xv cc , v cc = 5.5 v 200 a v in < 0.5xv cc , v cc = 3.3 v 150 v in < 0.5xv cc , v cc = 1.8 v 100 v in > 0.5xv cc 1 4. when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull ? down is relatively strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull ? down reverts to a weak current source.
cat24aa04, cat24aa08 http://onsemi.com 3 table 5. a.c. characteristics (note 5) (v cc = 1.7 v to 5.5 v, t a = ? 40 c to 85 c, unless otherwise speci ed.) symbol parameter standard v cc = 1.7 v ? 5.5 v fast v cc = 1.7 v ? 5.5 v 1 mhz v cc = 2.5 v ? 5.5 v units min max min max min max f scl clock frequency 100 400 1000 khz t hd:sta start condition hold time 4 0.6 0.25 s t low low period of scl clock 4.7 1.3 0.5 s t high high period of scl clock 4 0.6 0.5 s t su:sta start condition setup time 4.7 0.6 0.25 s t hd:dat data in hold time 0 0 0 ns t su:dat data in setup time 250 100 100 ns t r (note 6) sda and scl rise time 1000 300 300 ns t f (note 6) sda and scl fall time 300 300 100 ns t su:sto stop condition setup time 4 0.6 0.25 s t buf bus free time between stop and start 4.7 1.3 0.5 s t aa scl low to data out valid 3.5 0.9 0.4 s t dh data out hold time 100 50 50 ns t i (note 6) noise pulse filtered at scl and sda inputs 100 100 100 ns t su:wp wp setup time 0 0 0 s t hd:wp wp hold time 2.5 2.5 1 s t wr write cycle time 5 5 5 ms t pu (notes 6, 7) power ? up to ready mode 1 1 1 ms 5. test conditions according to ?a.c. test conditions? table. 6. tested initially and after a design or process change that affects this parameter. 7. t pu is the delay between the time v cc is stable and the device is ready to accept commands. table 6. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3 ma (v cc 2.5 v); i ol = 1 ma (v cc < 2.5 v); c l = 100 pf
cat24aa04, cat24aa08 http://onsemi.com 4 power ? on reset (por) each cat24aa04/08 incorporates power ? on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi ? directional por behavior protects the device against brown ? out failure, following a temporary loss of power. pin description scl: the serial clock input pin accepts the clock signal generated by the master. sda: the serial data i/o pin accepts input data and delivers output data. in transmit mode, this pin is open drain. data is acquired on the positive edge, and delivered on the negative edge of scl. wp: when the w rite protect input pin is forced high by an external source, all write operations are inhibited. when the pin is not driven by an external source, it is pulled low internally. functional description the cat24aa04/08 supports the inter ? integrated circuit (i 2 c) bus protocol. the protocol relies on the use of a master device, which provides the clock and directs bus traffic, and slave devices which execute requests. the cat24aa04/08 operates as a slave device. both master and slave can transmit or receive, but only the master can assign those roles. i 2 c bus protocol the 2 ? wire i 2 c bus consists of two lines, scl and sda, connected to the v cc supply via pull ? up resistors. the master provides the clock to the scl line, and the master and slaves drive the sda line. a ?0? is transmitted by pulling a line low and a ?1? by releasing it high. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, sda must remain stable while scl is high. start/stop condition an sda transition while scl is high creates a start or stop condition (figure 2). a start is generated by a high to low transition, while a stop is generated by a low to high transition. the start acts like a wake ? up call. absent a start, no slave will respond to the master. the stop completes all commands. device addressing the master addresses a slave by creating a start condition and then broadcasting an 8 ? bit slave address (figure 3). the four most significant bits of the slave address are 1010 (ah). the next three bits from the slave address byte are assigned as shown in figure 3, where a 9 and a 8 are internal address bits.the last bit, r/w , instructs the slave to either provide (1) or accept (0) data, i.e. it specifies a read (1) or a write (0) operation. acknowledge during the 9 th clock cycle following every byte sent onto the bus, the transmitter releases the sda line, allowing the receiver to respond. the receiver then either acknowledges (ack) by pulling sda low, or does not acknowledge (noack) by letting sda stay high (figure 4). bus timing is illustrated in figure 5. figure 2. start/stop timing start condition stop condition sda scl figure 3. slave address bits 101000a 8 r/w cat24aa04 10100a 9 a 8 r/w cat24aa08
cat24aa04, cat24aa08 http://onsemi.com 5 figure 4. acknowledge timing 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack setup ( t su:dat ) ack delay ( t aa ) figure 5. bus timing scl sda in sda out t buf t su:sto t su:dat t r t aa t dh t low t high t low t su:sta t hd:sta t hd:dat t f write operations byte write to write data to memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?0?. the master then sends an address byte and a data byte and concludes the session by creating a stop condition on the bus. the slave responds with ack after every byte sent by the master (figure 6). the stop starts the internal write cycle, and while this operation is in progress (t wr ), the sda output is tri ? stated and the slave does not acknowledge the master (figure 7). page write the byte w rite operation can be expanded to page w rite, by sending more than one data byte to the slave before issuing the stop condition (figure 8). up to 16 distinct data bytes can be loaded into the internal page write buffer starting at the address provided by the master. the page address is latched, and as long as the master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). new data can therefore replace data loaded earlier. following the stop, data loaded during the page write session will be written to memory in a single internal write cycle (t wr ). acknowledge polling the acknowledge (ack) polling routine can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operation, the cat24aa04/08 initiates the internal write cycle. the ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat24aa04/08 is still busy with the write operation, noack will be returned. if the cat24aa04/08 device has completed the internal write operation, an ack will be returned and the host can then proceed with the next read or write operation. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left oating or is grounded, it has no impact on the write operation. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the 1 st data byte (figure 9). if the wp pin is high during the strobe interval, the slave will not acknowledge the data byte and the write request will be rejected. delivery state the cat24aa04/08 is shipped erased, i.e., all bytes are ffh.
cat24aa04, cat24aa08 http://onsemi.com 6 figure 6. byte write sequence address byte data byte slave address s a c k a c k a c k s t o p p s t a r t bus activity: master slave * *a 9 = 0 for cat24aa04 a 9 a 8 a 7 a 0 d 7 d 0 figure 7. write cycle timing stop condition start condition address ack 8th bit byte n scl sda t wr figure 8. page write sequence a c k a c k a c k s t o p s a c k a c k s t a r t p slave address n = 1 address byte data byte n data byte n+1 data byte n+x bus activity: master slave * *a 9 = 0 for cat24aa04 a 9 a 8 a 7 a 0 d 7 d 0 x 15 figure 9. wp timing 189 1 8 address byte data byte scl sda wp t su:wp t hd:wp a 7 a 0 d 7 d 0
cat24aa04, cat24aa08 http://onsemi.com 7 read operations immediate read to read data from memory, the master creates a start condition on the bus and then broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack and starts shifting out data residing at the current address. after receiving the data, the master responds with noack and terminates the session by creating a stop condition on the bus (figure 10). the slave then returns to standby mode. selective read to read data residing at a speci c address, the selected address must rst be loaded into the internal address register. this is done by starting a byte w rite sequence, whereby the master creates a star t condition, then broadcasts a slave address with the r/w bit set to ?0? and then sends an address byte to the slave. rather than completing the byte write sequence by sending data, the master then creates a start condition and broadcasts a slave address with the r/w bit set to ?1?. the slave responds with ack after every byte sent by the master and then sends out data residing at the selected address. after receiving the data, the master responds with noack and then terminates the session by creating a stop condition on the bus (figure 11). sequential read if, after receiving data sent by the slave, the master responds with ack, then the slave will continue transmitting until the master responds with noack followed by st op (figure 12). during sequential read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory. figure 10. immediate read sequence and timing scl sda 8th bit stop no ack data out 89 slave address s a c k data byte n o a c k s t o p p s t a r t bus activity: master slave figure 11. selective read sequence slave s a c k n o a c k s t o p p s t a r t s a c k slave address a c k s t a r t data byte address byte address bus activity: master slave figure 12. sequential read sequence a c k a c k a c k s t o p n o a c k a c k p slave address data byte n data byte n+1 date byta n+2 data byte n+x bus activity: master slave
cat24aa04, cat24aa08 http://onsemi.com 8 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35
cat24aa04, cat24aa08 http://onsemi.com 9 package dimensions tsot ? 23, 5 lead case 419ae ? 01 issue o e1 e a2 a1 e b d c a top view side view end view l1 l l2 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-193. symbol min nom max a a1 a2 b c d e e1 e l 0o 8o l1 l2 0.01 0.80 0.30 0.12 0.30 0.05 0.87 0.15 2.90 bsc 2.80 bsc 1.60 bsc 0.95 typ 0.40 0.60 ref 0.25 bsc 1.00 0.10 0.90 0.45 0.20 0.50
cat24aa04, cat24aa08 http://onsemi.com 10 example of ordering information prefix device # suffix company id cat 24aa04 td product number 24aa04 i ? gt3 package i = industrial ( ? 40 c to +85 c) temperature range td: tsot ? 23 5 ? lead w: soic 8 ? lead t: tape & reel 3: 3,000 / reel 10: 10,000 / reel (note 11) lead finish g: nipdau blank: matte ? tin tape & reel (note 13) 24aa08 8. all packages are rohs-compliant (lead-free, halogen-free). 9. the standard lead finish is nipdau. 10. the device used in the above example is a cat24aa04tdi ? gt3 (tsot ? 23 5 ? lead, industrial temperature, nipdau, tape & reel, 3,000/reel). 11. the 10,000/reel option is only available for the tsot ? 23 5 ? lead package. 12. for additional package and temperature options, please contact your nearest on semiconductor sales office. 13. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. cat24aa04/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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